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GNU Toolchain for m68k / ColdFire

The kernel.org toolchains are currently adopted for development. Btw, at least for tested target mcf5307, both i686 and x86_64 kernel.org available toolchains have open issues.

Adopted toolchains

These toolchains has been tested building u-boot and running the generated binary on the target board.

Toolchain gcc binutils host version target cpu / board compile warnings notes
gcc-4.9.0-nolibc 2.26 x86_64 -m5307 / amcore no created with buildall script from kernel.org
gcc-5.2.0-nolibc 2.26 x86_64 -m5307 / amcore no created with buildall script from kernel.org

Note: we had issues building the toolchains with "--with-arch=cf" option, since compilation breaks:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68082
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68467
Without "--with-arch=cf", m68000 libgcc code is generated, breaking final binaries built with the toolchain when libgcc is used.

Since gcc team seems to keep m68k issues in a very low priority, these toolchains have the libgcc.a, libgcov.a and multilibs copied from an old toolchain.
If you experience any issue, use CONFIG_USE_PRIVATE_LIBGCC in your board config file.

Other bare-metal toolchains could be used, but note they can produce additional compile-time warnings in some cases, and u-boot code shouldn't be changed to remove the warnings in this cases.

Please report any issue to angelo @ sysam.it

See here for more information about toolchain-specific warnings:
https://lkml.org/lkml/2014/12/15/110
http://lists.denx.de/pipermail/u-boot/2014-December/199446.html

The discussion on how to avoid these "argument type" warnings with all tooolchains is still in progress.

ISA Revisions

As the Coldfire cpu evolved, some instruction set architecture revisions (note, not core revisions) has been issued, starting from the first, ISA_A, adding some instructions increasing the revision. Instruction sets are upward compatible.

ISA_A: it is the original Coldfire instruction set architecture, very similar to the m68000 instruction set
ISA_B: added improved data movement instructions, byte- and word-sized compares
miscellaneous enhancements
ISA_C: added instructions for improved bit manipulation

Below you can find what ISA Revision correspond to a cpu model.

Core V. CPU Model ISA_A ISA_A+ ISA_B ISA_C
1 mcf51qe       X
2 mcf5202 X      
2 mcf5204 X      
2 mcf5202 X      
2 mcf5204 X      
2 mcf5206 X      
2 mcf5208   X    
2 mcf52274   X    
2 mcf52277   X    
3 mcf5307 X      
3 mcf5329 X      
3 mcf5373 X      
4 mcf5407     X  
4 mcf5470     X  
4 mcf5471     X  
4 mcf5472     X  
4 mcf54450       X
4 mcf54451       X
4 mcf54452       X
4 mcf54453       X
4 mcf54454       X
4 mcf54455       X
4 mcf54450       X
4 mcf54451       X
4 mcf54452       X
4 mcf54453       X
4 mcf54454       X
4 mcf54455       X

Note that some obsolete model is possibly not reported in the table above.

TODOs

-- AngeloDureghello - 07 Jan 2015