;bdiGDB configuration file for TQM8548 ;---------------------------------------- ; ; Use default boot configuration: ; - Boot sequencer disabled ; - Boot from local bus 32-bit ROM ; [REGS] FILE BDI2000/reg8548.def ; [INIT] ; init core register ; ; define maximal transfer size ;TSZ4 0x00000000 0xffffffff ; ; HID1[ABE] should be set in 8540 ;WSPR 1009 0x00001000 ; ; Move the L2SRAM to the initial MMU page WM32 0xFF720000 0x68010000 ;L2CTL WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0 WM32 0xFF720000 0xA8010000 ;L2CTL ; ; load TLB entries, helper code @ 0xfffff000 WM32 0xfffff000 0x7c0007a4 ;tlbwe WM32 0xfffff004 0x7c0004ac ;msync WM32 0xfffff008 0x48000000 ;loop ; ; 16K mem WSPR 624 0x00000000 ;MAS0: WSPR 625 0x80000000 ;MAS1: WSPR 626 0xE4010000 ;MAS2: WSPR 627 0xE4010015 ;MAS3: EXEC 0xfffff000 WSPR 624 0x00000000 ;MAS0: WSPR 625 0x80000000 ;MAS1: WSPR 626 0xE4011000 ;MAS2: WSPR 627 0xE4011015 ;MAS3: EXEC 0xfffff000 WSPR 624 0x00000000 ;MAS0: WSPR 625 0x80000000 ;MAS1: WSPR 626 0xE4012000 ;MAS2: WSPR 627 0xE4012015 ;MAS3: EXEC 0xfffff000 WSPR 624 0x00000000 ;MAS0: WSPR 625 0x80000000 ;MAS1: WSPR 626 0xE4013000 ;MAS2: WSPR 627 0xE4013015 ;MAS3: EXEC 0xfffff000 ; ; 1MB TLB1 #1 0xE0000000 - 0xE00fffff WSPR 624 0x10010000 ;MAS0: WSPR 625 0x80000500 ;MAS1: WSPR 626 0xE000000a ;MAS2: WSPR 627 0xE0000015 ;MAS3: WSPR 628 0x00000000 ;MAS4: EXEC 0xfffff000 ; ; 64 MB TLB1 #4 0x04000000 - 0x07ffffff ;WSPR 624 0x10040000 ;MAS0: ;WSPR 625 0x80000800 ;MAS1: ;WSPR 626 0x04000008 ;MAS2: ;WSPR 627 0x04000015 ;MAS3: ;EXEC 0xfffff000 ; ; 256MB TLB1 #6 0x00000000 - 0x10000000 WSPR 624 0x10070000 ;MAS0: WSPR 625 0xc0000900 ;MAS1: WSPR 626 0x00000000 ;MAS2: WSPR 627 0x00000015 ;MAS3: EXEC 0xfffff000 ; ; 16 MB TLB1 #5 0xfe000000 - 0xfeffffff WSPR 624 0x10050000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xfe00000a ;MAS2: WSPR 627 0xfe000015 ;MAS3: EXEC 0xfffff000 ; ; 16 MB TLB1 #6 0xff000000 - 0xffffffff WSPR 624 0x10000000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xff00000a ;MAS2: WSPR 627 0xff000015 ;MAS3: EXEC 0xfffff000 ; WM32 0xFF720000 0x28010000 ;L2CTL WM32 0xFF720000 0x28000000 ;L2CTL ; ; Move CCSRBAR to 0x40000000 WM32 0xff700000 0x000E0000 ;CCSRBAR to 0xE0000000 ; ; Initialize LAWBAR's WM32 0xE0000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xE0000C10 0x80f0001c ;LAWAR0 : DDR/SDRAM 512MB WM32 0xE0000C28 0x000c0000 ;LAWBAR1 : @0xc0000000 WM32 0xE0000C30 0x8040001d ;LAWAR1 : Local Bus 1GB ; ; Setup DDR (512MB DDR) WM32 0xE0002000 0x0000001f ;CS0_BNDS WM32 0xE0002080 0x80000102 ;CS0_CONFIG WM32 0xE0002108 0x47445331 ;TIMING_CFG_1 WM32 0xE000210C 0x00000800 ;TIMING_CFG_2 WM32 0xE0002110 0xC2000000 ;DDR_SDRAM_CFG WM32 0xE0002118 0x40020062 ;DDR_SDRAM_MODE WM32 0xE0002124 0x05160100 ;DDR_SDRAM_IVAL DELAY 200 WM32 0xE0002110 0xC2000000 ;DDR_SDRAM_CFG ;WM32 0x00000f0 0x00000000 ;invalidate page table base ; ; Setup Flash chip select WM32 0xE0005000 0xc0001801 ;BR0 WM32 0xE0005004 0xf0000c54 ;OR0 ; ; Setup flash programming workspace in L2SRAM ;WM32 0xE0020000 0x68010000 ;L2CTL ;WM32 0xE0020100 0xf0000000 ;L2SRBAR0 ;WM32 0xE0020000 0xA8010000 ;L2CTL ;WSPR 63 0xf0000000 ;IVPR to workspace ;WSPR 415 0x0001500 ;IVOR15 : Debug exception ;WM32 0xf0001500 0x48000000 ;write valid instruction ; ; Setup flash programming workspace in dual port RAM ;WSPR 63 0x40080000 ;IVPR to workspace ;WSPR 415 0x000007F0 ;IVOR15 : Debug exception ;WM32 0xE00807F0 0x48000000 ;write valid instruction ; ; Setup for program execution WM32 0xE0020000 0x28010000 ;L2CTL WM32 0xE0020000 0x28000000 ;L2CTL WSPR 63 0x00000000 ;IVPR to workspace WSPR 406 0x0000700 ;IVOR6 : Program exception WSPR 415 0x0001500 ;IVOR15 : Debug exception WM32 0x00000700 0x48000000 ;write valid instruction WM32 0x00001500 0x48000000 ;write valid instruction ; ; Setup PCI express ;rm pexcfgaddr 0x8000005C ; ;rm pexcfgdata 0x00000020 ; ;rm pexcfgaddr 0x80000004 ; ;rm pexcfgdata 0x00000107 ; ;rm pexcfgaddr 0x80000018 ; ;rm pexcfgdata 0x00fe00ff ; [TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock STARTUP RUN ;don't use boot loop in L2SRAM ;STARTUP LOOP ;don't use boot loop in L2SRAM ;STARTUP HALT ;halt core while HRESET is asserted BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 1000 ;give reset time to complete ;POWERUP 5000 ;start delay after power-up detected in ms MEMACCESS CORE ;use SAP or CORE for JTAG memory accesses ;REGLIST E500 ;send registers in E500 sequence to GDB ; Kernel debugging options ;MMU XLAT ;PTBASE 0x000000f0 ;here is the pointer to the page table pointers [HOST] IP 10.0.30.1 LOAD MANUAL ;load code MANUAL or AUTO after reset FILE tqm8548/u-boot.dk FORMAT BIN 0x00200000 PROMPT TQM8548> [FLASH] CHIPTYPE MIRRORX16 ; für MIRROR-BIT FLASH CHIPSIZE 0x2000000 ;The size of one flash chip in bytes ;CHIPTYPE AM29BX16 ; für 4MByte Flashes (A016L) ;CHIPSIZE 0x1000000 ;The size of one flash chip in bytes BUSWIDTH 32 ;The width of the flash memory bus in bits (8 | 16 | 32) ;WORKSPACE 0x40080000 ;workspace in dual port RAM ;WORKSPACE 0xf0000000 ;workspace in L2SRAM ;WORKSPACE 0x100000 FILE tqm8548/u-boot.bin FORMAT BIN 0xC7F80000 ERASE 0xC7F80000 ERASE 0xC7FC0000
