- I am trying to single step into a Linux exception handler. This does not seem to work. Setting a breakpoint does not work either.
- The problem is bit complex on a MPC8xx target. Debug mode entry is like an exception and therefore only safe at locations in the code where exceptions does not lead to an unrecoverable state. Another exception can only be accepted if SRR0 and SRR1 are saved. The MSR[RI] should indicate if currently an exception is safe. MSR[RI] is cleared automatically at exception entry. The MPC8xx hardware breakpoints do only trigger if MSR[RI] is set in order to prevent non-recoverable state. The problem is that the Linux exception handler does not take all this into account. First priority has speed, therefore neither SRR0 nor SRR1 are saved immediately. Only after EXCEPTION_PROLOG this registers are saved. Also Linux does not handle the MSR[RI] bit. Hint: Use STEPMODE HWBP when debugging Linux. This allows the TLB Miss Exception handler to update the TLB while you are single stepping.
- You cannot debug Linux exception entry and exit code. Because of speed, DataStoreTLBMiss? does not even make use of EXCEPTION_PROLOG and SRR0/SRR1 are never saved. Therefore you cannot debug DataStoreTLBMiss? unless you change it's code (save SRR0/SRR1, set MSR[RI].
|14.6.1. Where can I find BDI2000 Configuration Files?||1. Abstract||14.6.3. How to single step through "RFI" instruction|