QONG FPGA Update using UrJtag
Abstract
This application note describes how to upgrade the FPGA with a new logic on the Freescale
i.MX31 based module
QONG module developed by
Dave Srl.
The upgrade is performed using the open source
UrJTAG Universal
JTAG tools.
Author
This document was written by Stefano Babic (sbabic {at} denx {dot} de).
Introduction
To offer maximum flexibility in each design, the QONG module combines
the i.MX31 with a powerful FPGA, which allows adaptable
I/O expansion as well as adding IP-cores for additional
customized interfaces.
To make use of this flexibility, it is necessary to install new
versions of the FPGA code by downloading a bitstream. Also, sometimes updated
versions of the FPGA code become available fixing problems and/or adding
new features.
Please note that the actual bitstream contains some core functionalities that
must be maintained. The bitstream delivered by Dave srl already contains
an Ethernet controller that is used as main controller in U-Boot and Linux.
The FPGA also contains a level shifter for the NAND flash.
If a redesigned FPGA does not provide these core features
neither Ethernet nor NAND flash will work.
On the QONG module, the required
JTAG pins of the FPGA
are connected to GPIO ports, so updates of the FPGA code can be done
in software, without using external tools like a dedicated
JTAG
programmer.
Instead of writing custom software for this purpose, we decided to use the
standard
UrJTAG Universal
JTAG tool.
Hardware configuration
It can be quite confusing to understand which FPGA can be updated as the evaluation
boards contain an additional FPGA. This guide refers
only to the FPGA present on the
QONG module and does not apply to the Qong-EvbLite board, where the QONG module
is integrated in the board itself and the FPGA is of a different type.
For the same reason, if you have a Qong-EVB this guide refers only to the FPGA on the module, not on the
motherboard. The QONG Module has an LFXP2 5E_FTBGA256 on board, while the boards
are populated with an LFXP217E 256 FPBGA. Do not try to download a bitstream to an FPGA of different type,
or you can damage your board. I am serious, this is not a joke.
More information about the different FPGAs mounted on the QONG products can be found on
the manufacturers site (
Lattice).
WARNING and LEGAL DISCLAIMER
Updating the FPGA code is a
very critical operation. First of
all, any attempts to meddle with the FPGA code will void any warranty you have. And if
anything goes wrong your board will be broken, and you will not be
able to fix it.
There is absolutely, positively
NO WARRANTY, neither express or
implied, offered with this documentation and software. You use this
documentation and software at your own risk. In case of loss, no
person or entity owes you anything whatsoever. You have been warned.
You have been warned!
How to generate the required SVF file
urjtag supports bitstreams in SVF format and if the file you generated is in another
format, you must convert it before applying. The manufacturer offers a free tool for development and conversion
between different formats (
ispvmsystem).
Attached you will find the SVF file for the delivered bitstream. Please pay attention that
the tool provided by lattice extends the SVF language using some non-standard commands,
that are not interpreted by urjtag. This applies to the LOOP/ENDLOOP commands, which must be expanded
into the complete list of statements.
Also attached is a simple script to convert the LOOP/ENDLOOP statements. The resulting file can
be successfully interpreted by urjtag.
To get the SVF from your generated jedec file, start the ispvm tool (follow the instructions you find
on the manufacturer site).
- Start a new project
- From the Edit menu, click on Add device.
- In the dialog box, set the device as shown in the following picture. You must add the QONG FPGA to ispvm project and you
must select the LFXP2-5E device.
- Now in the same dialog box add your jedec file, or the file delivered by Dave:
- Now click on Project->generate SVF file, and click on "Build SVF file for a single device".
The tool should now generate a "quite" ready file for urjtag. If you open the file with an editor,
you will find some comments that advise you about the incompatibility with the LOOP/ENDLOOP statements.
You must also comment out the Frequency statement, as frequency will be set with urjtag.
Now run the simple svf_to_urjtag.pl script attached to this page. This generates
an SVF file compatible with urjtag.
For example, if qong-5C5-0.8.7.jed.svf is the output of the ispvsim tool, do the following:
./svf_to_urjtag.pl < qong-5C5-0.8.7.jed.svf > qong-5C5-0.8.7.svf
Compiling and installing urjtag for QONG module
The gpio cable driver, required to drive some GPIOs as
JTAG interface, is integrated
in the actual urjtag tree. If you get urjtag via git, you do not need to apply the patch.
Compiling and installing actual urjtag
Get sources via git from the
UrJTAG home site.
You still need to apply the patch to recognize the Lattice FPGA.
$ patch -p1 < 0002-Add-definition-files-for-Lattice-XFP2-5e-256-FPGA.patch
$ autoreconf
$ ./configure --disable-bus --without-libusb --host=arm-linux --target=arm-linux --enable-cable=gpio
$ make
$ make DESTDIR=<PATH_TO_INSTALL> install
Applying the patch to urjtag 0.10
On your host, download the urjtag tool and apply the patches in attachment:
$ wget http://surfnet.dl.sourceforge.net/sourceforge/urjtag/urjtag-0.10.tar.bz2
$ tar xjf urjtag-0.10.tar.bz2
$ cd urjtag-0.10
$ patch -p1 < 0001-Support-updating-FPGA-on-QONG-module.patch
$ patch -p1 < 0002-Add-definition-files-for-Lattice-XFP2-5e-256-FPGA.patch
$ autoreconf
Now you are ready to cross-compile the tool. Set up for using the
ELDK toolchain as usual.
$ ./configure --disable-bus --without-libusb --host=arm-linux --target=arm-linux --enable-cable=qong_gpio
$ make
$ make DESTDIR=<PATH_TO_INSTALL> install
Notes installing on root filesystem
You now have the urjtag tools in the subdirectory usr/local starting from the path you have chosen.
You have to put this stuff on your rootfilesystem. Please be aware that:
- Because the FPGA contains the Ethernet controller, you cannot use a NFS server as rootfilesystem.
Network is not available during the update process.
- NAND Flash is not availbale, too. You must put your rootfilesystem containing urjtag
in a RAM disk or on the NOR flash. NAND will become unavailable after the uploading process is started.
- install the SVF file you generated on your rootfilesystem, so it can be used on the target
Starting the UrjTag tool on the QONG module
on the target, you can start the jtag command:
-bash-3.2# ./jtag
UrJTAG 0.10 #1502
Copyright (C) 2002, 2003 ETC s.r.o.
Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors
UrJTAG is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
There is absolutely no warranty for UrJTAG.
Now you can enable the qong module:
For 0.10 Version:
jtag> cable qong_gpio
Initializing QONG GPIO JTAG Chain
qong_init:
If you use the actual urjtag sources
jtag> cable gpio tdo=7 tdi=8 tck=26 tms=25
Initializing GPIO JTAG Chain
gpio_init:
As you see, the driver in the actual tree has no reference anymore to the QONG module
and can be used on any system with available GPIOs to drive the
JTAG interface and
you are able to configure the meaning of the gpios at runtime.
Detecting the FPGA
jtag> detect
IR length: 8
Chain length: 1
Device Id: 00000001001010011001000001000011 (0x0000000001299043)
Manufacturer: Lattice Semiconductors
Part(0): LFXP2-5E-FTBGA256
Stepping: 0
Filename: /usr/local/share/urjtag/lattice/lfxp2-5e_ftbga256/lfxp2_5e_ftbga256
If detect does not work, do not try with the following commands. With detect, you can check
if the jtag connection to the FPGA is working. The tool must report the FPGA ID as described here.
Setting the frequency
Now set the frequency. As you can see, I sets the frequency more than one time. It seems that computed frequency is
always smaller the first time is set. Normally, there is no reason to set it multiple times and the following log
will only show that the frequency remains constant after it is set for the second time.
jtag> frequency
Current TCK frequency is 0 Hz
jtag> frequency 1000000
Setting TCK frequency to 1000000 Hz
requested frequency 1000000, now calibrating delay loop
new real frequency 53508, delay 0
operating without delay
done
jtag> frequency 1000000
Setting TCK frequency to 1000000 Hz
requested frequency 1000000, now calibrating delay loop
new real frequency 60695.9, delay 0
operating without delay
done
jtag> frequency 1000000
Setting TCK frequency to 1000000 Hz
requested frequency 1000000, now calibrating delay loop
new real frequency 60696.3, delay 0
operating without delay
done
jtag> print
No. Manufacturer Part Stepping Instruction Register
------------------------------------------------------------------------------------------------------------------
0 Lattice Semiconductors LFXP2-5E-FTBGA256 0 BYPASS BYPASS
Dowloading the FPGA bitstream
You can now start the update with the svf command:
jtag> svf <your_svf_file> progress
At the beginning there are some expected errors, do not care about them. The real update starts when the progress
is shown as percentage. No error is expected after that.
If everything is fine, you will get the message
Scanned device output matched expected TDO values.
Now power cycle the system and check if the update was okay as currently only the flash on the FPGA
was updated, but not the SRAM containing the logic.
If everything is ok, you will see U-Boot running reporting the new FPGA version:
U-Boot 2010.03-00172-g133734b-dirty (Apr 28 2010 - 13:49:18)
CPU: Freescale i.MX31 at 398 MHz
Board: DAVE/DENX Qong
DRAM: 128 MB
Flash: 32 MB
NAND: 128 MiB
In: serial
Out: serial
Err: serial
FPGA: version register = 0.8.7
Net: dnet0
Hit any key to stop autoboot: 0
If the version reported is 15.15.255, your FPGA is still unprogrammed. This means that u-boot reads only 0xFF
when tries to access to the version register (or to any other register in FPGA). In this situation, network and
NAND are not working. Try to repeat the procedure to restore the FPGA.
