SDRAM - Synchronous Dynamic RAM
SDRAM has become ubiquitous for relatively fast, inexpensive read/write memory (RAM). The
SDRAM interface was created/adopted/popularized by Intel with the Pentium
TM class processors. Its number one distinguishing feature is that it pipelines commands (
e.g. read/write operations) using a state machine. Thus the processor has a state machine in its
SDRAM controller logic and the
SDRAM has its internal state machine. In order to have
both state machines in lock-step operation, the
SDRAM has configuration registers that need to be initialized by the processor using special configuration cycles. The resulting start up code that initializes the
SDRAM registers looks pretty odd and entirely mysterious.
If the
SDRAM initialization is not done
exactly as required by the
SDRAM's data sheet, the processor's data sheet, and taking into account bus speeds,
etc., the processor's memory controller and the
SDRAM state machines will get out of sync. The result is unreliable memory operations, particularly burst reads and writes. Note that simple and even moderately complex memory read and write operations will appear to work, but when the processor starts using the pipelining heavily (typically due to lots of cache read and write activity and
DMA activity), the two will lose synchronization and cause memory read/write errors.
